1. Field of the Invention
The present invention relates in general to electrical interconnect systems for linking integrated circuit chips and in particular to an interconnect system employing a vertical signal path along an edge of an integrated circuit chip.
2. Description of Related Art
FIG. 1 is a simplified sectional elevation view of a prior art interconnect system for linking two integrated circuits (ICs) 12 and 14 mounted on a printed circuit board (PCB) 10. IC 12 includes an integrated circuit chip 16 contained within an IC package 18. A bond pad 20 on the surface of chip 16 acts as an input/output (I/O) terminal for signals entering and/or departing chip 16. A typical IC will include several bond pads, but for simplicity only one is shown in FIG. 1. A bond wire 22 links bond pad 20 to a package pin 24 extending outward from package 18. Pin 24 is soldered onto a microstrip trace 25 on the surface of PCB 10. Bond wire 22 and pin 24 together form a path for conveying signals between bond pad 20 and PCB trace 25. A bond pad 26 in IC 14 is connected to microstrip trace 25 in a similar manner through a bond wire 27 and a package pin 28.
A signal traveling between the bond pads of the two ICs 12 and 14 thus traverses an interconnect system 29 comprising two bond wires 22 and 27, two package pins 24 and 28, and trace 25. Since interconnect system 29 delays the signal in proportion to its signal path length, we can reduce the interconnect system's signal path delay by reducing its length. For example, we can make bond wires 22 and 27, pins 24 and 28, and trace 25 as short as possible to reduce signal path delay in the interconnect system of FIG. 1. However, since pads 20 and 26 reside in different IC packages there is a limit to how short we can make the signal path.
Hybrid Circuits
FIG. 2 is a simplified sectional elevation view of a prior art hybrid circuit interconnect system containing four unpackaged IC chips 32 directly mounted on a PCB 30. ICs 32 communicate with one another through signal paths comprising only bond wires 34 and microstrip traces 36. Since IC chips 32 are not separately packaged, the hybrid circuit interconnect system eliminates package pins from all signal paths between the chips thereby reducing interconnect system length and signal path delay.
FIG. 3 is a simplified sectional elevation view of a prior art “flip-chip” hybrid circuit wherein IC chips 42 are mounted face-down on a PCB 40. FIG. 3A illustrates in greater detail a region 44 of FIG. 3 wherein solder balls 46, when melted, attach bond pads 48 of one IC chip 42 to microstrip traces 50 residing on PCB 40. Alternatively, spring contacts 52 (FIG. 3B) can connect bond pads on IC chip 42 to traces 50. The flip-chip interconnect system further reduces signal path lengths and delays by eliminating bond wires from signal paths between ICs.
FIG. 4 is a simplified sectional elevation view of a prior art “stacked” flip-chip hybrid circuit 70 wherein an IC chip 78 is mounted directly on another IC chip 76 residing on a PCB 72. Solder 84 links bond pads 63 and 64 of IC chips 76 and 78. Bord wires 86 link bond pads 65 on IC chip 76 to microstrip traces 88 on PCB 72. The “stacked” flip-chip interconnect system eliminates bond wires and traces from signal paths between two ICs. However it still requires bond wires to connect more than two ICs since normally only two ICs can be directly linked to one another.
Electrical Through-Wafer Interconnects
Electrical Through-Wafer Interconnect (ETWIs) systems enable stacking of more than two IC chips by employing conductive “vias” routing electrical signals vertically through IC chips.
FIG. 5 is a simplified sectional elevation view of a hybrid circuit 90 containing a stack 94 of IC chips 96(1)-96(3) interconnected by a set of vias 92 passing vertically through the substrates of IC chips 96(1)-96(3) and linking bond pads 109 and 108 residing on upper and lower surfaces of the IC chips. Stack 94 resides on a PCB 100 having a set of microstrip traces 102. Solder 106 directly links bond pads 109 on IC under sides to bond pads 108 on the top sides of adjacent IC chips or to traces 102 on PCB 100. The ETWI system thus eliminates bond wires from connecting between several ICs 96.
FIGS. 6A-6E are simplified partial sectional views illustrating a prior art method for forming a via through an IC substrate 110. In FIG. 6A a patterned resist layer 116 coats an upper surface 112 of IC substrate 110 exposing an area 118 in which an ETWI is to be formed. Area 118 is isotropically etched (FIG. 6B) to form a void 111 having walls 117 in substrate 110. Each etch step (FIG. 6B) is followed by a passivation step (FIG. 6C) wherein the walls 117 of void 111 are passivated to prevent further etching of these surfaces to form a high-aspect ratio hole. In FIG. 6C a protective layer 115 is photo-lithographically formed on a lower surface 119 of void 111. After formation of layer 115 a passivation gas is introduced to void 111 to passivate walls 117 of void 111 and form a passivation layer 113. Layer 115 prevents the passivation of lower surface 119 and is removed after each passivation step to expose that surface to further etching.
For a typical IC substrate 110 having a thickness of greater than 1000 microns, the etch and passivation steps of FIGS. 6B-6C must be repeated many times to form a high aspect-ratio hole 120 of FIG. 6D extending completely through substrate 110. After forming hole 120, resist layer 116 (FIGS. 6A-6D) is removed and a conductive layer 122 is formed (FIG. 6D) on substrate 110 filling hole 120. Portions of layer 122 are then removed photo-lithographically to yield an ETWI 124 extending between upper and lower surfaces 112 and 114 of substrate 110 as illustrated in FIG. 6E.
FIGS. 7A-7F are simplified partial sectional views illustrating an alternative prior art method for forming an ETWI. A patterned resist layer 136 coats an upper surface 132 of an IC substrate 130 exposing an area 138 of that upper surface. The exposed area 138 of upper surface 132 is then etched several times (FIGS. 7B-7C) in a manner similar to that described above for FIGS. 6B-6C. However the process is halted after forming a shallow hole 140 that does not extend completely through substrate 130. Thereafter substrate 130 is “thinned” (FIG. 7E) by etching a lower surface 134 of substrate 130 in a blanket or bulk fashion so that hole 140 passes through the thinned substrate 130. The bulk etching step of FIG. 7E does not require photolithography techniques and therefore is relatively inexpensive. As illustrated in FIG. 7F, the resist layer 136 (FIGS. 7A-7D) is removed from substrate 130 and a conductive layer 142 is formed thereon completely filling hole 140 of FIG. 7E. Portions of layer 142 are then removed photo-lithographically to yield an ETWI 144 extending between upper and lower surfaces 132 and 134 of substrate 130 through hole 140.
The lithographically-defined etching techniques described above can make small diameter, high aspect-ratio holes but these techniques are slow and expensive. Less expensive techniques such as laser or mechanical drilling produce large holes that take up too much surface area in the IC.
What is needed is an economical system for quickly forming vertical signal paths in an IC substrate that do not occupy space on the substrate that could otherwise be used for IC components.